(a) Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices. More particularly, the present invention relates to a method for forming an aluminum contact in a semiconductor device.
(b) Description of the Related Art
As semiconductor devices have been more highly integrated, width and thickness of metal lines therein have been reduced, and size of a contact has been reduced. Therefore, an aspect ratio of a contact hole has been increased, and thus a method for fully filling the contact hole has become very important.
For a method for fully filling the contact hole having a high aspect ratio with a low resistivity material, an aluminum layer may be deposited by a chemical vapor deposition (CVD) process, so-called Al-CVD.
The Al-CVD process is classified as a blanket deposition process or a selective deposition process. The blanket deposition process is a method of filling a contact hole by depositing an aluminum film on an entire surface of a wafer. This process is for making the best of a good step-coverage of the aluminum film. However, the blanket deposition process of Al-CVD may have an abnormal growth characteristic in a thick aluminum film. Consequently, the film may have a rough surface and may fail to fill a small contact due to blocking of an inlet portion.
On the other hand, the selective deposition process is a method for making use of a difference of a growth rate depending on a substrate (e.g., an insulation layer or a conductive layer) whereon the deposition is performed. This process can be used for a limited region such as a via contact, but it has a difficulty in forming a metal contact wherein a barrier metal is pre-deposited.
Japanese Patent Publication No. 1992-171940 describes a manufacturing method of a semiconductor device including steps of forming conductive layers having an ohmic conductive layer and a barrier conductive layer and a aluminum layer (or aluminum alloy layer) in a contact hole, leaving the aluminum layer in a sidewall of the contact hole, leaving the barrier conductive layer on the bottom of the contact hole, reflowing the aluminum layer in a sidewall of the contact hole, and forming an additional aluminum layer to fill the contact hole. Additionally, U.S. Pat. No. 6,022,800 describes a method of filling a contact hole including steps of forming a first TiN layer on an entire surface of a contact hole by a CVD method, forming a second TiN layer thereon by a physical vapor deposition (PVD), and forming a tungsten layer so as to fill the contact hole. Furthermore, Japanese Patent Publication No. 1998-64902 describes a method of a filling a contact hole including steps of forming a barrier layer of Ti and TiN by a PVD method, forming a Ti layer on the barrier layer, forming an aluminum layer at room temperature, and reflowing the aluminum layer by a thermal process.
As the line width in a circuit becomes narrower, conventional deposition methods for aluminum wiring in a semiconductor device face limitations. Accordingly, a method for filling a contact hole (a contact between a lower conductive layer and an upper aluminum line) or a via hole (a contact between a lower aluminum line and an upper aluminum line) has become a critical technology for an electrical interconnection.
In filling the contact hole or via hole (referred to as only “contact hole” hereinafter) with aluminum, various process methods have been developed so as to have better electrical characteristics and better filling characteristics. In manufacturing a next generation memory device, the contact hole has a high aspect ratio, so a PVD method (i.e., a sputtering method) becomes insufficient for a deposition process for forming a metal layer having a line width of under 0.25 μm. Therefore, various types of research are under investigation for forming an aluminum layer using a CVD method having a better step coverage characteristic than the PVD method. Particularly, a process is under investigation wherein an aluminum thin film is selectively formed in a contact hole by a CVD method and an additional aluminum layer is deposited on an exterior part of the contact hole.
FIG. 1A and FIG. 1B are cross-sectional views showing principal stages of forming an aluminum contact according to a conventional method.
First, as shown in FIG. 1A, an active region is defined on a silicon wafer 101 by a field oxide layer (not shown). The field oxide layer is formed by using a local oxidation of silicon (LOCOS) process or a trench process. A gate oxide layer 104 is formed on the silicon wafer 101 by a thermal oxidation process. Subsequently, a polysilicon layer 106 to be used as a gate electrode is formed on the gate oxide layer 104, and the polysilicon 106 and the gate oxide layer 104 are patterned to a predetermined width.
Then, a lightly doped drain (LDD) 103 is formed in an active region on the silicon wafer 101 by implanting P-type or N-type dopants having a low concentration thereinto by using the gate electrode 106 as an implantation mask. After a liner layer 107 and a sidewall 105 is sequentially formed on both side of the gate stack including the oxide layer 104 and the gate electrode 106, a source/drain 102 is formed in an active region on the silicon wafer 101 by implanting the same type of dopants as the LDD 103 thereinto by using the sidewall 105 and gate electrode 106 as an implantation mask.
Subsequently, after a capping oxide layer 108 is formed on the upper surface of the substrate, a pre-metal dielectric (PMD) layer 109 composed of ozone-TEOS or high density plasma phosphosilicate glass (HDP-PSG) is thickly formed by an atmospheric pressure CVD (APCVD) method. After a heat treatment process for improving the hardness of the PMD layer 109, the upper surface of the PMD layer is planarized by chemical mechanical polishing (CMP). Then, a capping oxide layer 110 is formed on the PMD layer 109.
After a photosensitive layer pattern (not shown) for patterning a contact hole is formed on the capping oxide layer 110, as shown in FIG. 1B, the contact hole is formed by etching the exposed capping oxide layer 110 by using the photosensitive layer pattern as a etching mask. The contact hole is filled by depositing a TiN layer 111 as a barrier metal layer on the entire surface over the silicon wafer 101 and subsequently forming a tungsten layer 112.
A tungsten layer formed by a CVD method has relatively low resistivity. In addition, tungsten is a heavy metal having high immunity against electron migration and stress migration, and thus the tungsten layer may be free from voids or hillocks that may cause a junction breakdown. However, as the integration of semiconductor devices become higher, a metal having a low resistivity is highly required. Aluminum having a low resistivity has a difficulty in suppressing a hillock, and thus junction breakdown may occur.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form a part of the prior art with respect to the present invention.